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19-1040; Rev 0; 10/07
KIT ATION EVALU BLE AVAILA
Single Quick-PWM Step-Down Controller with Dynamic REFIN
General Description Features
o Quick-PWM with Fast Transient Response o Supports Any Output Capacitor No Compensation Required with Polymers/Tantalum Stable with Ceramic Output Capacitors Using External Compensation o Precision 2V 10mV Reference o Dynamically Adjustable Output Voltage (0 to 0.9 x VIN Range) Feedback Input Regulates to 0 to 2V REFIN Voltage 0.5% VOUT Accuracy Over Line and Load o 26V Maximum Input Voltage Rating o Resistively Programmable Switching Frequency o Undervoltage/Thermal Protection o Voltage Soft-Start and Soft-Shutdown o Monotonic Power-Up with Precharged Output o Power-Good Window Comparator
MAX17024
The MAX17024 pulse-width modulation (PWM) controller provides high efficiency, excellent transient response, and high DC-output accuracy needed for stepping down high-voltage batteries to generate lowvoltage core or chipset/RAM bias supplies in notebook computers. The output voltage can be controlled using the dynamic REFIN, which supports input voltages between 0 to 2V. The REFIN adjustability combined with a resistive voltage-divider on the feedback input allows the MAX17024 to be configured for any output voltage between 0 to 0.9 x VIN. Maxim's proprietary Quick-PWMTM quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios (low-duty-cycle applications) with ease and provides 100ns "instant-on" response to load transients while maintaining a relatively constant switching frequency. Strong drivers allow the MAX17024 to efficiently drive large synchronous-rectifier MOSFETs. The controller senses the current across the sense resistor series with the synchronous rectifier to achieve highly accurate valley current-limit protection. The MAX17024 includes a voltage-controlled soft-start and soft-shutdown to limit the input surge current, provide a monotonic power-up (even into a precharged output), and provide a predictable power-up time. The controller also includes output undervoltage and thermal-fault protection. The MAX17024 is available in a tiny 14-pin, 3mm x 3mm TDFN package. For space-constrained applications, refer to the MAX17016 single step-down with 26V internal MOSFETs capable of supporting 10A continuous load. The MAX17016 is available in a small 40-pin, 6mm x 6mm TQFN package.
Ordering Information
PART PIN-PACKAGE PKG CODE TOP MARK
MAX17024ETD 14 TDFN-EP* 3mm x 3mm T1433-1 ADO Note: This device is specified over the -40C to +85C operating temperature range.
+Denotes a lead-free package. *EP = Exposed paddle.
Pin Configuration
PGOOD REFIN
Applications
Notebook Computers I/O and Chipset Supplies GPU Core Supply DDR Memory--VDDQ or VTT Point-of-Load Applications Step-Down Power Supply
VCC
REF
CS 9
EN
14
13
12
11
10
MAX17024
GND
1 VDD 2 DL 3 N.C. 4 LX 5 DH 6 BST 7 TON
TDFN (3mm x 3mm)
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
FB 8
TOP VIEW
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
ABSOLUTE MAXIMUM RATINGS
TON to GND ...........................................................-0.3V to +28V VDD to GND ..............................................................-0.3V to +6V VCC to GND ................................................-0.3V to (VDD + 0.3V) EN, PGOOD to GND.................................................-0.3V to +6V REF, REFIN to GND ....................................-0.3V to (VCC + 0.3V) CS, FB to GND ...........................................-0.3V to (VCC + 0.3V) DL to GND ..................................................-0.3V to (VDD + 0.3V) BST to GND .................................................(VDD - 0.3V) to +34V BST to LX..................................................................-0.3V to +6V BST to VDD .............................................................-0.3V to +28V DH to LX ....................................................-0.3V to (VBST + 0.3V) REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 14-Pin 3mm x 3mm TDFN (derated 24.4mW/C above +70C)....................1951mW Operating Temperature Range (extended) .........-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 1)
PARAMETER PWM CONTROLLER Input Voltage Range Quiescent Supply Current (VDD) Shutdown Supply Current (VDD) VDD-to-VCC Resistance On-Time Minimum Off-Time TON Shutdown Supply Current REFIN Voltage Range REFIN Input Current FB Voltage Range VREFIN IREFIN VFB VIN IDD + ICC I SHDN RCC t ON t OFF(MIN) VIN = 12V, VFB = 1.0V (Note 3) (Note 3) EN = GND, VTON = 26V, VCC = 0V or 5V, TA = +25C (Note 2) REFIN = 0.5V to 2V, TA = +25C (Note 2) VREFIN = 0.5V, measured at FB, VIN = 2V to 26V TA = 0C to +85C FB Voltage Accuracy VFB VREFIN = 1.0V VREFIN = 2.0V FB Input Bias Current FB Output Low Voltage Load-Regulation Error Line-Regulation Error Soft-Start/Stop Slew Rate Dynamic REFIN Slew Rate SSSR DYNSR IFB I SINK = 3mA VCS = 2mV to 20mV VCC = 4.5V to 5.5V, VIN = 4.5V to 26V Rising/falling edge on EN Rising edge on REFIN 0.4 3 0.1 0.25 1.2 9.45 2.2 18 TA = +25C TA = 0C to +85C TA = 0C to +85C TA = +25C 0 -50 0 0.495 0.493 0.995 0.993 1.990 -0.1 2.0 1.0 0.5 RTON = 97.5k (600kHz) 118 250 354 RTON = 200k (300kHz) RTON = 302.5k FB forced above REFIN EN = GND, TA = +25C 2 0.7 0.1 20 139 278 417 200 0.01 160 306 480 300 1 VREF +50 VREF 0.505 0.507 1.005 1.007 2.010 +0.1 0.4 A V % % mV/s mV/s V ns A V nA V ns 26 1.2 2 V mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
0.5V to 2.0V, TA = +25C
2
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 1)
PARAMETER REFERENCE Reference Voltage FAULT DETECTION With respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mV Upper PGOOD Trip Threshold VPGOOD_H Dynamic transition Minimum V PGOOD_H threshold Lower PGOOD Trip Threshold Output Undervoltage Fault-Propagation Delay PGOOD Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current Dynamic REFIN Transition Fault Blanking Threshold Thermal-Shutdown Threshold VCC Undervoltage Lockout Threshold CURRENT LIMIT Current-Limit Threshold Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) CS Input Current VCS VINEG VZX ICS VGND - VCS VCS = 200mV, TA = +25C -1 18 20 -24 1 +1 22 mV mV mV A T SHDN VUVLO(VCC) I PGOOD With respect to the internal target voltage VPGOOD_L (error comparator threshold) falling edge; hysteresis = 50mV tUVP FB forced 25mV below V PGOOD_L trip threshold VPGOOD_L falling edge, 25mV overdrive t PGOOD VPGOOD_H rising edge, 25mV overdrive Startup delay I SINK = 3mA FB = REFIN (PGOOD high impedance), PGOOD forced to 5V, TA = +25C Fault blanking initiated; REFIN deviation from the internal target voltage (error comparator threshold); hysteresis = 10mV Hysteresis = 15C Rising edge, PWM disabled below this level; hysteresis = 100mV 3.95 50 160 4.2 4.45 100 -240 250 300 VREF + 0.30 0.7 -200 -160 mV 350 mV VREF VCC = 4.5V to 5.5V No load IREF = -10A to +50A 1.990 1.98 2.00 2.00 2.010 2.02 V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17024
V
100
200 5 5 200
350
s
s 350 0.4 1 V A
mV C V
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3
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 1)
PARAMETER GATE DRIVERS DH Gate Driver On-Resistance DL Gate Driver On-Resistance DH Gate Driver Source/ Sink Current DL Gate Driver Source Current DL Gate Driver Sink Current Driver Propagation Delay DL Transition Time DH Transition Time Internal BST Switch On-Resistance INPUTS AND OUTPUTS EN Logic-Input Threshold EN Logic-Input Current VEN I EN EN rising edge, hysteresis = 450mV (typ) EN forced to GND or VDD, TA = +25C 1.20 -0.5 1.7 2.20 +0.5 V A RBST R ON(DH) R ON(DL) IDH BST - LX forced to 5V High state (pullup) Low state (pulldown) DH forced to 2.5V, BST - LX forced to 5V Low state High state (pullup) 1.2 1.2 1.7 0.9 1.5 1 2.4 10 15 25 35 20 20 20 20 4 7 3.5 3.5 4 2 A A A ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
IDL(SOURCE) DL forced to 2.5V IDL(SINK) DL forced to 2.5V DH low to DL high DL low to DH high DL falling, CDL = 3nF DL rising, CDL = 3nF DH falling, CDH = 3nF DH rising, CDH = 3nF IBST = 10mA, VDD = 5V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA = -40C to +85C, unless otherwise specified.) (Note 1)
PARAMETER PWM CONTROLLER Input Voltage Range Quiescent Supply Current (VDD) On-Time Minimum Off-Time REFIN Voltage Range FB Voltage Range VIN IDD + ICC t ON t OFF(MIN) VREFIN VFB FB forced above REFIN VIN = 12V, VFB = 1.0V (Note 3) (Note 3) (Note 2) (Note 2) VREFIN = 0.5V Measured at FB, VREFIN = 1.0V VIN = 2V to 26V VREFIN = 2.0V I SOURCE = 3mA 0 0 0.49 0.99 1.985 RTON = 97.5k RTON = 200k RTON = 302.5k (600kHz) (300kHz) (200kHz) 115 250 348 2 26 1.2 163 306 486 350 VREF VREF 0.51 1.01 2.015 0.4 V V ns V V ns V mA SYMBOL CONDITIONS MIN MAX UNITS
FB Voltage Accuracy
VFB
FB Output Low Voltage
4
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA = -40C to +85C, unless otherwise specified.) (Note 1)
PARAMETER REFERENCE Reference Voltage FAULT DETECTION Upper PGOOD Trip Threshold With respect to the internal target voltage VPGOOD_H (error comparator threshold) rising edge; hysteresis = 50mV With respect to the internal target voltage VPGOOD_L (error comparator threshold) falling edge; hysteresis = 50mV tUVP FB forced 25mV below V PGOOD_L trip threshold I SINK = 3mA VUVLO(VCC) Rising edge, PWM disabled below this level, hysteresis = 100mV 3.95 250 350 mV VREF VDD = 4.5V to 5.5V 1.985 2.015 V SYMBOL CONDITIONS MIN MAX UNITS
MAX17024
Lower PGOOD Trip Threshold Output Undervoltage Fault-Propagation Delay PGOOD Output Low Voltage VCC Undervoltage Lockout Threshold CURRENT LIMIT Current-Limit Threshold GATE DRIVERS DH Gate Driver On-Resistance DL Gate Driver On-Resistance Internal BST Switch On-Resistance INPUTS AND OUTPUTS EN Logic-Input Threshold
-240
-160
mV
80
400 0.4 4.45
s V V
VCS BST - LX forced Low state (pulldown) to 5V High state (pullup) High state (pullup) Low state (pulldown) IBST = 10mA, VDD = 5V EN rising edge hysteresis = 450mV (typ)
17
23 3.5 3.5 4 2 7
mV
R ON(DH) R ON(DL) RBST VEN
1.20
2.20
V
Note 1: Limits are 100% production tested at TA = +25C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 2: The 0 to 0.5V range is guaranteed by design, not production tested. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds.
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5
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
Typical Operating Characteristics
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200k, TA = +25C, unless otherwise noted.)
1.5V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX17024 toc01
1.5V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17024 toc02
1.05V OUTPUT EFFICIENCY vs. LOAD CURRENT
95 90 EFFICIENCY (%)
MAX17024 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0.01 0.1 1.0 12V 20V 7V
1.53
100 7V
OUTPUT VOLTAGE (V)
1.52
85 80 75 70 65 12V 20V
1.51
1.50 10 0.01 0.1 1 10 LOAD CURRENT (A) LOAD CURRENT (A)
60 0.01 0.1 1.0 10 LOAD CURRENT (A)
1.05V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17024 toc04
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17024 toc05
SWITCHING FREQUENCY vs. TEMPERATURE
MAX17024 toc06
1.060
350 300 250 200 150 100 50 VIN = 12V VOUT = 1.5V
360 ILOAD = 10A 350
1.058 OUTPUT VOLTAGE (V)
1.056
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
340
1.054
ILOAD = 5A
1.052
330 VIN = 12V VOUT = 1.5V -40 -20 0 20 40 60 80 100
1.050 0.01 0.1 1 10 LOAD CURRENT (A)
0 0.01 0.1 1 10 LOAD CURRENT (A)
320 TEMPERATURE (C)
MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE
11.2 MAXIMUM OUTPUT CURRENT (A) 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 6 9 12 15 18 21 24 INPUT VOLTAGE (V) VOUT = 1.5V 10.0 -40
MAX17024 toc07
MAXIMUM OUTPUT CURRENT vs. TEMPERATURE
MAX17024 toc08
NO-LOAD SUPPLY CURRENT IBIAS vs. INPUT VOLTAGE
MAX17024 toc09
11.4
12.0 MAXIMUM OUTPUT CURRENT (A)
0.80 0.70 0.60
11.5 IBIAS (mA)
11.0
0.50 0.40
10.5 0.30 VOUT = 1.5V 0.20 -20 0 20 40 60 80 100 6 8 10 12 14 16 18 20 22 24 TEMPERATURE (C) INPUT VOLTAGE (V) VOUT = 1.5V
6
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Typical Operating Characteristics (continued)
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200k, TA = +25C, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT IIN vs. INPUT VOLTAGE
MAX17024 toc10
MAX17024
REF OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17024 toc11
REFIN-TO-FB OFFSET VOLTAGE DISTRIBUTION
+85C SAMPLE PERCENTAGE (%) 40 +25C SAMPLE SIZE = 100
MAX17024 toc12
0.20 0.18 0.16 0.14 IIN (mA) 0.12 0.10 0.08 0.06 0.04 0.02 0 6 8 10 12 14 16 18 20 22 VOUT = 1.5V
2.000 1.999 REF OUTPUT VOLTAGE (V) 1.998 1.997 1.996 1.995 1.994 1.993 1.992 1.991
50
30
20
10
-2.5
-2.0
-1.5
-1.0
-0.5
0
1.990 24 -10 0 10 20 30 40 50 INPUT VOLTAGE (V) LOAD CURRENT (A)
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
CURRENT-LIMIT THRESHOLD VOLTAGE DISTRIBUTION
+85C SAMPLE PERCENTAGE (%) 40 +25C SAMPLE SIZE = 100
MAX17024 toc13
SOFT-START WAVEFORM (HEAVY LOAD)
MAX17024 toc14
SOFT-START WAVEFORM (LIGHT LOAD)
MAX17024 toc15
50
5V 0 5V 0 1.5V 0 6A 0
A
5V 0 5V 0
2.5 A B C D
B
30
20
C
1.5V 0
10
D 0 200s/div C. VOUT, 1V/div D. INDUCTOR CURRENT, 10A/div
18.0
18.4
18.8
19.2
19.6
20.0
20.4
20.8
21.2
21.6
22.0
0
CS THRESHOLD VOLTAGE (mV)
A. EN, 5V/div B. PWRGD, 5V/div IOUT = 6A
A. EN, 5V/div B. PWRGD, 5V/div IOUT = 1A
200s/div C. VOUT, 1V/div D. INDUCTOR CURRENT, 10A/div
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7
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
Typical Operating Characteristics (continued)
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200k, TA = +25C, unless otherwise noted.)
SHUTDOWN WAVEFORM
MAX17024 toc16
LOAD-TRANSIENT RESPONSE
MAX17024 toc17
5V 0 5V 0 5V 0 1.5V 0 A B C
8A 1A 1.53V A
1.49V 10A
B
D 0A 0 200s/div D. VOUT, 1V/div E. INDUCTOR CURRENT, 5A/div E 20s/div C. INDUCTOR CURRENT, 5A/div C
A. EN, 5V/div B. PWRGD, 5V/div C. DL, 5V/div IOUT = 6A
A. IOUT 10A/div B. VOUT, 20mV/div
IOUT = 1A TO 8A TO 1A
OUTPUT OVERLOAD WAVEFORM
MAX17024 toc18
DYNAMIC OUTPUT-VOLTAGE TRANSITION
MAX17024 toc19
14A 0 A 1.5V 0 5V 0 5V 0 200s/div A. INDUCTOR CURRENT, C. DL, 5V/div 10A/div D. PGOOD, 5V/div B. VOUT, 1V/div IOUT = 2A TO 14A D B
1.5V 1.05V 1.5V B 1.05V 10A C 0 12V D 0 A. REFIN, 500mV/div B. VOUT, 200mV/div IOUT = 2A 40s/div C. INDUCTOR CURRENT, 10A/div D. LX, 10V/div C A
8
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Pin Description
PIN 1 2 3 4 5 6 NAME VDD DL N.C. LX DH BST FUNCTION Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1F or greater ceramic capacitor. Low-Side Gate Driver. DL swings from GND to VDD. The MAX17024 forces DL low during VCC UVLO and REFOK lockout conditions. Not Connected Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1. High-Side Gate Driver. DH swings from LX to BST. The MAX17024 pulls DH low whenever the controller is disabled. Boost Flying-Capacitor Connection. Connect to an external 0.1F 6V capacitor as shown in Figure 1. The MAX17024 contains an internal boost switch/diode (see Figure 2). Switching Frequency-Setting Input. An external resistor between the input power source and TON sets the switching period (TSW = 1 / f SW) according to the following equation: 7 TON
V TSW = CTON (RTON + 6.5k) FB VOUT
MAX17024
where CTON = 16.26pF and VFB = VREFIN under normal operating conditions. If the TON current drops below 10A, the MAX17024 shuts down and enters a high-impedance state. TON is high impedance in shutdown. Feedback Voltage-Sense Connection. Connect directly to the positive terminal of the output capacitors for output voltages less than 2V as shown in Figure 1. For fixed-output voltages greater than 2V, connect REFIN to REF and use a resistive divider to set the output voltage (Figure 4). FB senses the output voltage to determine the on-time for the high-side switching MOSFET. Current-Sense Input Pin. Connect to low-side MOSFET current-sense resistor. The current-limit threshold is 20mV (typ). External Reference Input. REFIN sets the feedback regulation voltage (VFB = VREFIN) of the MAX17024 using the resistor-divider connected between REF and GND. The MAX17024 includes an internal window comparator to detect REFIN voltage transitions, allowing the controller to blank PGOOD and the fault protection. 2V Reference Voltage. Bypass to analog ground using a 470pF to 1nF ceramic capacitor. The reference can source up to 50A for external loads. Shutdown Control Input. Connect to VDD for normal operation. Pull EN low to place the controller into its 2A shutdown state. When disabled, the MAX17024 slowly ramps down the target/output voltage to ground and after the target voltage reaches 0.1V, the controller forces both DH and DL low and enters the low-power shutdown state. Toggle EN to clear the fault-protection latch. 5V Analog Supply Voltage. Internally connected to VDD through an internal 20 VCC to analog ground using a 1F ceramic capacitor. resistor. Bypass
8
FB
9
CS
10
REFIN
11
REF
12
EN
13
VCC
14
PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 200mV (typ) below or 300mV (typ) above the target voltage (VREFIN) during soft-start and soft-shutdown. After the soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation. PGOOD is blanked--forced high-impedance state--when a dynamic REFIN transition is detected. Ground/Exposed Pad. Internally connected to the controller's ground plane and substrate. Connect directly to ground.
EP (15)
GND
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9
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
5V BIAS SUPPLY 1 C1 4.7F C2 1F AGND PWR 13 R4 100k 14 ON OFF C3 1nF 12 PGOOD EN CS VCC LX DL VDD TON BST 7 6 5 4 2 9 RCS 2m 8 PWR CBST 0.1F L1 RTON 200k CIN PWR OUTPUT 1.05V/1.50V 10A (MAX) COUT PWR INPUT 7V TO 24V
MAX17024 DH
D1
11
REF FB
AGND R3 97.6k AGND LO HI AGND
R1 49.9k 10 R2 54.9k REFIN GND (EP)
AGND
PWR
Figure 1. MAX17024 Standard Application Circuit
Table 1. Component Suppliers
MANUFACTURER AVX BI Technologies Central Semiconductor Coiltronics Fairchild Semiconductor International Rectifier KEMET NEC Tokin WEBSITE www.avxcorp.com www.bitechnologies.com www.centralsemi.com www.cooperet.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokin.com
MANUFACTURER Panasonic Pulse Renesas SANYO Siliconix (Vishay) Sumida Taiyo Yuden TDK TOKO Toshiba Wurth WEBSITE www.panasonic.com www.pulseeng.com www.renesas.com www.edc.sanyo.com www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.toshiba.com www.we-online.com
Standard Application Circuit
The MAX17024 standard application circuit (Figure 1) generates a 1.5V or 1.05V output rail for general-purpose use in a notebook computer. Table 1 lists the component manufacturers.
Detailed Description
The MAX17024 step-down controller is ideal for the low-duty-cycle (high-input voltage to low-output voltage) applications required by notebook computers.
10
Maxim's proprietary Quick-PWM pulse-width modulator in the MAX17024 is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency, current-mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time (regardless of input voltage) PFM control schemes.
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
+5V Bias Supply (VCC/VDD) The MAX17024 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's main 95% efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator, such as the MAX1615. The 5V bias supply powers both the PWM controller and internal gate drive, so the maximum current drawn is determined by:
TON ON-TIME COMPUTE
IBIAS = IQ + fSWQG = 2mA to 20mA (typ) The MAX17024 includes a 20 resistor between VDD and VCC, simplifying the PCB layout request.
MAX17024
Free-Running Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor's ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a
IN OUT Q
tOFF(MIN) TRIG ONE-SHOT
BST
tON TRIG ONE-SHOT
S Q INTEGRATOR (CCV) R
Q
DH LX
ERROR AMPLIFIER
VDD S Q R DL
FB EA + 0.3V ZERO CROSSING
GND
PGOOD AND FAULT PROTECTION
CS VALLEY CURRENT LIMIT
REF EA - 0.2V EN SOFTSTART/STOP EA 2V REF VCC
PGOOD
REFIN
BLANK
MAX17024
DYNAMIC OUTPUT TRANSITION DETECTION
Figure 2. MAX17024 Functional Block Diagram
______________________________________________________________________________________ 11
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
one-shot whose pulse width that is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (200ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out.
Power-Up Sequence (POR, UVLO)
The MAX17024 is enabled when EN is driven high, and the 5V bias supply (V DD) is present. The reference powers up first. Once the reference exceeds its UVLO threshold, the internal analog blocks are turned on and masked by a 50s one-shot delay to allow the bias circuitry and analog blocks enough time to settle to their proper states. With the control circuitry reliably powered up, the PWM controller may begin switching. Power-on reset (POR) occurs when VCC rises above approximately 3V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC exceeds 4.25V, and EN is driven high. With the reference in regulation, the controller ramps the output voltage to the target REFIN voltage with a 1.2mV/s slew rate: t START = VFB VFB = 1.2mV / s 1.2V / ms
On-Time One-Shot The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to input and output voltage. The high-side switch on-time is inversely proportional to the input voltage as sensed by the TON input, and proportional to the feedback voltage as sensed by the FB input: On-Time (tON) = TSW (VFB / VIN)
where TSW (switching period) is set by the resistance (RTON) between TON and VIN. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. Connect a resistor (RTON) between TON and VIN to set the switching period TSW = 1 / fSW: V TSW = CTON (RTON + 6.5k) FB VOUT where CTON = 16.26pF. When used with unity-gain feedback (VOUT = VFB), a 96.75k to 303.25k corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. For continuous conduction operation, the actual switching frequency can be estimated by: fSW = VFB + VDIS t ON (VIN - VCHG +VDIS)
The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PGOOD becomes high impedance approximately 200s after the target REFIN voltage has been reached. The MAX17024 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling EN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low).
Shutdown
When the system pulls EN low, the MAX17024 enters low-power shutdown mode. PGOOD is pulled low immediately, and the output voltage ramps down with a 1.2mV/s slew rate: t SHDN = VFB VFB = 1.2mV / s 1.2V / ms
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the resistances in the charging path, including the highside switch, inductor, and PCB resistances; and tON is the on-time calculated by the MAX17024.
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Slowly discharging the output capacitors by slewing the output over a long period of time (typically 0.5ms to 2ms) keeps the average negative inductor current low (damped response), thereby preventing the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17024 shuts down completely--the drivers are disabled (DL and DH pulled low)--the reference turns off, activates 10 pulldown on FB, and the supply currents drop to about 0.1A (typ). When a fault condition--output UVP or thermal shutdown--activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle EN or cycle VCC power below 0.5V. The MAX17024 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown. the load current and output capacitance. Letting the output voltage drift down is typically recommended to reduce the potential for audible noise since this eliminates the input current surge during negative outputvoltage transitions.
MAX17024
Valley Current-Limit Protection
The current-limit circuit employs a unique "valley" current-sensing algorithm that senses the inductor current through the low-side MOSFET sense resistor. If the current through the low-side MOSFET exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and input voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance.
Integrated Output Voltage
The MAX17024 regulates the valley of the output ripple, so the actual DC output voltage is higher than the slopecompensated target by 50% of the output ripple voltage. Under steady-state conditions, the MAX17024's internal integrator corrects for this 50% output ripple-voltage error, resulting in an output voltage accuracy that is dependent only on the offset voltage of the integrator amplifier provided in the Electrical Characteristics table.
Automatic Pulse-Skipping The MAX17024 permanently operates in automatic skip mode. An inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator threshold is set by the differential across the low-side MOSFET sense resistor. The controller automatically transitions to fixed-frequency PWM operation when the load reaches the same critical condition point (ILOAD(SKIP)) that occurs at the skip and the PWM boundary. DC output-accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX17024 regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Since the output is not able to sink current, the timing for negative dynamic output-voltage transitions depends on
Dynamic Output Voltages The MAX17024 regulates FB to the voltage set at REFIN. By changing the voltage at REFIN (Figure 1), the MAX17024 can be used in applications that require dynamic output-voltage changes between two set points. For a step-voltage change at REFIN, the rate of change of the output voltage is limited either by the internal 9.45mV/s slew-rate circuit or by the component selection--inductor current ramp, the total output capacitance, the current limit, and the load during the transition--whichever is slower. The total output capacitance determines how much current is needed to change the output voltage, while the inductor limits the current ramp rate. Additional load current may slow down the output voltage change during a positive REFIN voltage change, and may speed up the output voltage change during a negative REFIN voltage change.
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13
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
5V BIAS SUPPLY 1 C1 4.7F PWR C2 1F 13 AGND R4 100k 14 PGOOD LX 4 VCC 7 RTON 332k CIN BST 6 CBST 0.1F DH 5 L1 PWR INPUT 7V TO 24V
VDD
TON
MAX17024
OUTPUT 3.3V R6 13.0k COUT PWR
DL
2
ON
OFF C3 1nF
12
EN
CS
9 RCS
11
REF FB 8 PWR
AGND 10 REFIN GND (EP)
R7 20.0k AGND
AGND
PWR
Figure 3. High Output-Voltage Application Using a Feedback Divider
Output Voltages Greater than 2V Although REFIN is limited to a 0 to 2V range, the output-voltage range is unlimited since the MAX17024 utilizes a high-impedance feedback input (FB). By adding a resistive voltage-divider from the output to FB to analog ground (Figure 3), the MAX17024 supports output voltages above 2V. However, the controller also uses FB to determine the on-time, so the voltage-divider influences the actual switching frequency, as detailed in the On-Time One-Shot section.
Internal Integration An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This internal amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output-voltage regulation regardless of the compensated feedback ripple voltage and internal slope-compensation variation. The integrator amplifier has the ability to shift the output voltage by 55mV (typ). The MAX17024 disables the integrator by connecting the amplifier inputs together at the beginning of all downward REFIN transitions done in pulse-skipping mode. The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Power-Good Outputs (PGOOD) and Fault Protection
PGOOD is the open-drain output that continuously monitors the output voltage for undervoltage and overvoltage conditions. PGOOD is actively held low in shutdown (EN = GND) during soft-start and soft-shutdown. Approximately 200s (typ) after the soft-start terminates, PGOOD becomes high impedance as long as the feedback voltage is above the PGOOD_L threshold (REFIN - 200mV) and below the PGOOD_H threshold (REFIN + 300mV). PGOOD goes low if the feedback voltage drops 200mV below the target voltage (REFIN) or rises 300mV above the target voltage (REFIN), or the SMPS controller is shut down. For a logic-level PGOOD output voltage, connect an external pullup resistor between PGOOD and VDD. A 100k pullup resistor works well in most applications. Figure 4 shows the power-good and fault-protection circuitry.
Thermal-Fault Protection (TSHDN) The MAX17024 features a thermal fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down the controller. Both DL and DH are pulled low. Toggle EN or cycle VCC power below VCC POR to reactivate the controller after the junction temperature cools by 15C.
MAX17024
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate driver (DH) sources and sinks 1.5A, and the low-side gate driver (DL) sources 1.0A and sinks 2.4A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET driver is powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency.
PGOOD When the feedback voltage drops 200mV below the target voltage (REFIN), the controller immediately pulls PGOOD low and triggers a 200s one-shot timer. If the feedback voltage remains below the VPGOOD_L threshold for the entire 200s, the undervoltage fault latch is set and the SMPS begins the shutdown sequence. When the internal target voltage drops below 0.1V, the MAX17024 forces DL low. Toggle EN or cycle V CC power below V CC POR to clear the fault latch and restart the controller.
POWER-GOOD AND FAULT PROTECTION
TARGET - 200mV
TARGET + 300mV FB
EN SOFT-START COMPLETE ONESHOT 200s UV FAULT LATCH UV FAULT VPGOOD_H
VPGOOD_L
POWER-GOOD
IN CLK
OUT
Figure 4. Power-Good and Fault Protection
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Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17024 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.9 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high-input voltages and long inductive driver traces must ensure rising LX edges do not pull up the low-side MOSFETs' gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS CISS Typically, adding a 4700pF between DL and power ground (C NL in Figure 5), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 5). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
BST (RBST)* INPUT (VIN) CBST DH LX NH L
VDD
CBYP
DL (CNL)* PGND
NL
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 5. Gate Drive Circuit
adapter voltage. The minimum value (V IN(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current: There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Most notebook loads generally exhibit ILOAD = ILOAD(MAX) x 80%. Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical.
Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case input supply voltage allowed by the notebook's AC *
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
* Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. The amount of overshoot due to stored inductor energy when the load is removed can be calculated as: VSOAR
MAX17024
(ILOAD(MAX) )2L
2COUT VOUT
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the inductor ripple current (IL), therefore: ILIMIT(LOW) > ILOAD(MAX) - IL 2
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VOUT VIN - VOUT L= fSWILOAD(MAX)LIR VIN Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + IL 2
where ILIMIT(LOW) equals the minimum current-sense threshold voltage (see the Electrical Characteristics table) divided by the low-side MOSFET sense resistance RCS.
Output Capacitor Selection
The output filter capacitor must have low-enough effective series resistance (ESR) to meet output ripple and load-transient requirements. Additionally, the ESR impacts stability requirements. Capacitors with a high ESR value (polymers/tantalums) do not need additional external compensation components. In core and chipset converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can be determined by:
T 2 V L( ILOAD(MAX) ) OUT SW + t OFF(MIN) VIN VSAG = (VIN - VOUT )TSW 2COUT VOUT - t OFF(MIN) VIN
(RESR + RPCB ) I
VSTEP
LOAD(MAX)
In low-voltage applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. The maximum ESR to meet ripple requirements is: VIN fSW L RESR VRIPPLE (VIN - VOUT )VOUT where fSW is the switching frequency.
where tOFF(MIN) is the minimum off-time (see the Electrical Characteristics table).
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
With most chemistries (polymer, tantalum, aluminum electrolytic), the actual capacitance value required relates to the physical size needed to achieve low ESR and the chemistry limits of the selected capacitor technology. Ceramic capacitors provide low ESR, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Thus, the output capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. ESR vs. voltage rating) and cost. See Figure 6. For a standard 300kHz application, the effective zero frequency must be well below 95kHz, preferably below 50kHz. With these frequency requirements, standard tantalum and polymer capacitors already commonly used have typical ESR zero frequencies below 50kHz, allowing the stability requirements to be achieved without any additional current-sense compensation. In the standard application circuit (Figure 1), the ESR needed to support a 15mVP-P ripple is 15mV / (10A x 0.3) = 5m. Two 330F, 9m polymer capacitors in parallel provide 4.5m (max) ESR and 1 / (2 x 330F x 9m) = 53kHz ESR zero frequency. See Figure 7.
MAX17024
Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the in-phase feedback ripple relative to the switching frequency, which is typically dominated by the output ESR. The boundary of instability is given by the folowing equation: fSW 1 2REFFCOUT REFF = RESR + RPCB + RCOMP
where COUT is the total output capacitance, RESR is the total equivalent-series resistance of the output capacitors, RPCB is the parasitic board resistance between the output capacitors and feedback sense point, and RCOMP is the effective resistance of the DC- or AC-coupled current-sense compensation (see Figure 8).
TON BST DH L1 LX MAX17024 DL CS RCS FB GND AGND PWR PWR
INPUT CIN PWR
OUTPUT COUT PWR
STABILITY REQUIREMENT 1 RESRCOUT 2fSW
Figure 6. Standard Application with Output Polymer or Tantalum
TON BST DH L1 MAX17024 LX DL CS CCOMP 0.1F CIN PWR
INPUT
PCB PARASITIC RESISTANCE SENSE RESISTANCE FOR EVALUATION
OUTPUT COUT PWR RCOMP 100 OUTPUT VOLTAGE REMOTELY SENSED NEAR POINT OF LOAD CLOAD PWR
FB GND AGND PWR PWR STABILITY REQUIREMENT 1 1 RESRCOUT AND RCOMPCCOMP 2fSW fSW FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
Figure 7. Remote-Sense Compensation for Stability and Noise Immunity
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Ceramic capacitors have a high-ESR zero frequency, but applications with sufficient current-sense compensation can still take advantage of the small size, low ESR, and high reliability of the ceramic chemistry. Using the inductor DCR, applications using ceramic output capacitors can be compensated using either a DCcompensation or AC-compensation method (Figure 8).
OPTION A: DC-COUPLED CURRENT-SENSE COMPENSATION TON BST DH L LX DL MAX17024 CS CSEN FB GND AGND PWR PWR STABILITY REQUIREMENT RSENA RSENB COUT PWR OUTPUT CIN PWR INPUT DC COMPENSATION <> FEWER COMPENSATION COMPONENTS <> CREATES OUTPUT LOAD LINE <> LESS OUTPUT CAPACITANCE REQUIRED FOR TRANSIENT RESPONSE
The DC-coupling requires fewer external compensation capacitors, but this also creates an output load line that depends on the inductor's DCR (parasitic resistance). Alternatively, the current-sense information may be ACcoupled, allowing stability to be dependent only on the inductance value and compensation components and eliminating the DC load line.
MAX17024
((
R R 1 L C AND LOAD LINE = SENB DCR RSENA || RSENB) CSEN OUT 2fSW RSENA + RSENB
)
FEEDBACK RIPPLE IN-PHASE WITH INDUCTOR CURRENT OPTION B: AC-COUPLED CURRENT-SENSE COMPENSATION TON CIN BST DH L LX DL MAX17024 CS CCOMP FB GND AGND PWR PWR STABILITY REQUIREMENT RCOMP RSEN CSEN COUT PWR OUTPUT PWR INPUT AC COMPENSATION <> NOT DEPENDENT ON ACTUAL DCR VALUE <> NO OUTPUT LOAD LINE
(R
L
SENCSEN
)
COUT
1 1 AND RCOMPCCOMP 2fSW fSW
FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
Figure 8. Feedback Compensation for Ceramic Output Capacitors
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value may allow significant output overshoot when stepping from full-load to no-load conditions, unless designed with a small inductance value and high switching frequency to minimize the energy transferred from the inductor to the capacitor during load-step recovery. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedbackloop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX17024
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V IN(MIN) and V IN(MAX) . Calculate both these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the maximum efficiency occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Drivers section).
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation: I IRMS = LOAD VOUT (VIN - VOUT ) VIN The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
20
MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:
V PD (NH Re sistive) = OUT (ILOAD )2RDS(ON) VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high-input voltages. However, the RDS(ON) required to stay within packagepower dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: QG(SW) PD (NH Switching) = VIN(MAX)ILOAD fSW + IGATE COSS VIN(MAX)2 fSW 2 where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.4A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: V 2 PD (NL Re sistive) = 1- OUT (ILOAD ) RDS(ON) VIN(MAX) The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "overdesign" the circuit to tolerate: I ILOAD = IVALLEY(MAX) + L 2 ILOAD(MAX)LIR = IVALLEY(MAX) + 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side, MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFETs' gates: CBST = N x QGATE 200mV
MAX17024
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 x 24nC = 0.24F 200mV
Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
Minimum Input-Voltage Requirements and Dropout Performance
The output voltage-adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time settings. When working with low-input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Transient Response section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP / IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used.
21
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Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: V - VDROOP + VCHG VIN(MIN) = FB 1 - h x t OFF(MIN)fSW
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. * Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the VCC bypass capacitor, REF bypass capacitors, REFIN components, and feedback compensation/dividers. Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (REF, REFIN, FB).
(
)
where VFB is the voltage-positioning droop, VCHG, is the parasitic voltage drop in the charge path, and tOFF(MIN) is from the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout design example: VFB = 1.5V fSW = 300kHz tOFF(MIN) = 350ns No droop/load line (VDROOP = 0) VDROPCHG = 150mV (10A load) h = 1.5: 1.5V - 0V + 150mV VIN(MIN) = = 1.96V 1- (1.5 x 350ns x 300kHz) Calculating again with h = 1 gives the absolute limit of dropout: 1.5V - 0V + 150mV VIN(MIN) = = 1.84V 1- (1.0 x 350ns x 300kHz) Therefore, VIN must be greater than 1.84V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 2.0V.
*
*
*
*
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST capacitors, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figure 1. This diagram can be viewed as having 4 separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the GND pin and VDD bypass capacitor go; the controller's analog ground plane where sensitive analog components, the controller's GND pin, and VCC bypass capacitor go. The controller's ground plane must meet the power ground plane only at a single point directly beneath the IC (this si done automatically inside the MAX17024 through the back pad). These ground planes should connect to the high-power output ground with a short metal trace from GND (back pad) to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
MAX17024
Chip Information
TRANSISTOR COUNT: 7169 PROCESS: BiCMOS
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23
Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17024
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
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Single Quick-PWM Step-Down Controller with Dynamic REFIN
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX17024
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
PACKAGE VARIATIONS PKG. CODE T633-2 T833-2 T833-3 T1033-1 T1033-2 T1433-1 T1433-2 N 6 8 8 10 10 14 14 D2 1.500.10 1.500.10 1.500.10 1.500.10 1.500.10 1.700.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEED-3 MO229 / WEED-3 ------b 0.400.05 0.300.05 0.300.05 0.250.05 0.250.05 0.200.05 0.200.05 [(N/2)-1] x e 1.90 REF 1.95 REF 1.95 REF 2.00 REF 2.00 REF 2.40 REF 2.40 REF
0.25 MIN. 0.20 REF.
Note: MAX17024ETD+ Package Code = T1433-1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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